1. Field of the Invention
The present invention is generally concerned with digital transmission.
The present invention is more particularly concerned with filtering dejustification jitter of a digital bit stream, i.e. the jitter caused by eliminating from the received bit stream justification bits inserted during its formation for matching the timing of an unjustified digital bit stream to be transmitted to the timing at which it is to be transmitted.
The present invention is more particularly applicable to digital bit streams formed using the positive justification technique which is used if the timing of the unjustified digital bit stream to be transmitted has a lower nominal value than the timing with which it is to be transmitted.
The present invention is therefore applicable to timing adaptation in a plesiochronous transmission network.
The invention is therefore also applicable to timing adaptation at the input of a synchronous transmission network and in particular of a synchronous transmission network transmitting digital bit streams formed in accordance with the synchronous multiplexing hierarchy defined in CCITT Recommendations G.707, G.708 and G.709.
2. Description of the Prior Art
The timing of an unjustified digital bit stream can be recovered at the receiving end from a positive justified digital bit stream after eliminating the justification bits from the latter. A known method for this uses a phase-locked loop to slave the rate at which a buffer memory is read to the rate at which the buffer memory is written by the incoming digital bit stream, after elimination of its justification bits. This method uses low-pass filtering.
The problem arises that the jitter due to positive dejustification includes very low frequency components which cannot be eliminated by this method.
The present invention can provide a solution to this problem.